Kea V41N Series
The KEA V4.1NA GNSS receiver is an FPGA based receiver platform ideally suited as a working receiver or as a reference design for teaching, research or further product development. It is a small form-factor receiver designed for pin compatibility with other OEM GPS receivers.
The KEA receiver features an Altera CycloneTM 5E FPGA and with embedded memory and phase locked loop circuitry. The receiver firmware runs on the Altera NIOS 32 bit RISC soft core processor. The GNSS base-band logic is also contained in the CycloneTM 5E FPGA. The receiver architecture is designed to allow multiple NIOS soft core processors to operate in the same FPGA if required. There is additional unused logic capacity in the FPGA for expansion and development.
The receiver is delivered as a working GNSS receiver and can be customised to any end user requirements on request.
The RF down-converter uses a custom wide band ASIC to convert the GNSS signal to a low 4MHz IF for sampling. It allows access to both GPS L1 and Galileo E1 signals.
This receiver model contains an Altera 5CEA4 Cyclone V FPGA with 49K logic elements. There is also 1MByte of static RAM.
This receiver model contains an Altera 5CEA45 Cyclone V FPGA with 77K logic elements. There is also 64MByte of dynamics RAM.
This receiver model contains an Altera 5CEA47 Cyclone V FPGA with 149K logic elements. There is also 64MByte of dynamics RAM.
To meet specific end user requirements the firmware and base band can be customised to include features such as carrier phase measurement and or special output messages on request.